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2009, Microelectronic Engineering
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2008, MELECON 2008 - The 14th IEEE Mediterranean Electrotechnical Conference
Scaling beyond the 45 nm technology node requires high-κ dielectrics to suppress gate leakage current which, in turn, demands metal gates. In this paper, bulk FinFET with high-κ/metal gate stack, such as HfO 2/TiN, and bulk FinFET with SiO 2/poly-Si gate stack were analyzed and compared by 3D device simulation. The influence of using high-κ dielectric and metal gate on subthreshold and on-s tate device performance is examined. HfO 2/TiN FinFET with the dielectric thickness of 2 nm has excellent performa nce, both in subthreshold and saturation (drain-induced barrier lowering of 29 mV/V, subthreshold swing of 91 mV/dec, drive current of 2670 µA/µm, and gate leakage under 0.02 A/cm 2). A major limitation is the intrinsic switching speed of only 365 GHz, when compared to the conventional SiO 2/poly-Si FinFET with the same dielectric thickness (1167 GHz).
2012, International Journal of Computer Applications
FinFETs are popular in complex circuit applications due to excellent scalability and better short channel effects. Bottom spacer FinFET concept is used to achieve improved short-channel and reduced self-heating issues to solve width quantization effect. Fully depleted dual material concept provides novel features like threshold voltage roll-up, transconductance enhancement and suppression of short channel effects by work function engineering. Further, to reduce coupling of electric field between source and drain and hence reducing drain induces barrier lowering (DIBL), ground plane concept is introduced. Figures of merit (FOM) such as transconductance (gm), output conductance (gd), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cutoff frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are systematically presented for different active fin height using 3-D simulation of dual material ground plane bottom spacer FinFET.
Active and Passive Electronic Components
Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for dev...
2011, International Conference on Ultimate Integration of Silicon
A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant
2011, Solid-State Electronics
2010, Microelectronic Engineering
In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages; (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from the (1 1 0) surface; (iii) higher variability due to the non-uniform fin extension doping, as highlighted by applying a novel characterization technique.
2008, Solid-State Electronics
This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-κ dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained ...
2007
This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs (I–V, C–V and 1/f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/f noise) and saturation region (normalized transconductance, early
2020
Bioelectric impedances have been found to correlate with a number of biological phenomena in some tissues, organs, and cells. This has helped to advance several of today's bioelectric impedance applications, like Electrical Impedance Tomography (EIT), Electrical impedance spectroscopy (EIS). For calculating bioelectric impedance it is very important to design low power Analog Front end consisting of Op-amp and ADC. In this paper, a low supply voltage based FinFET operational amplifier and its characteristics are studied and designed by using Cadence 18nm FinFET technology. The standard characteristics of the opamp like gain, bandwidth, unity gain bandwidth product, settling time and so on are distinguished with the existing architectures. The suggested FinFET-based amplifiers are having a greater performance at a reduced voltage than conventional two-stage Op-amps. In this work, supply voltage is provided as 0.8V. The circuit consumes a power of 35 μW, provides a gain of 83 dB a...
Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials
In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size...
2010, … IEEE Transactions on
International Journal on Smart Sensing and Intelligent Systems
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However, as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
International Journal of Computer Theory and Engineering
2000, IEEE Transactions on Electron Devices
2000, IEEE Transactions on Electron Devices
2021, International Journal for Research in Applied Science & Engineering Technology
Now days, Nano scale devices are in demand due to their higher packing density and high performance in microelectronics circuits. Tri-gate Junctionless N-channel FinFET provides better performance at nano scale regime. This paper analyzes the effects of channel doping concentration on electrical parameter of Tri-gate Junctionless N-channel FinFET. Different important device electrical parameter such as ON current, OFF current, I ON /I OFF , Threshold voltage, Subthreshold slope, DIBL. Results show that as the channel doping concentration of the Tri-gate Junctionless N-channel FinFET the threshold voltage (V TH) decreases. Besides, the drain-induced barrier lowering and the subthreshold swing of the Tri-gate Junctionless N-channel FinFET become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I OFF) increases and the on-current (I ON) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. Results show that for short channel devices the better performance is obtained with smaller channel doping concentration with higher I ON /I OFF and smaller values of Subthreshold slope, DIBL.
2016, Solid-State Electronics
2009, Selected Topics in Electronics and Systems
2007, IEEE Transactions on Electron Devices
An analytical physically based analysis for undoped FinFET devices in the subthreshold and near-threshold regimes has been developed by solving the 3-D Poisson equation, in which the mobile-charge term was included. From this analysis, a subthreshold-swing model has been developed; this model is also based on a new physically based analysis of the conduction path. The subthreshold-swing model has been
2008, Microelectronic Engineering
2000, IEEE Transactions on Electron Devices
2008, Microelectronic Engineering
2015, Communications on Applied Electronics
Journal of Low Power Electronics
2016
As the dimensions of transistors shrink, the close proximity between the source and drain reduces the ability of the gate electrode to control the potential distribution and the flow of current in the channel region because of which undesirable short channel effects starts plugging in MOSFETs. For all practical reasons, it seems to be impossible to scale the dimensions of classical bulk MOSFETs below 20nm. To satisfy Moore’s law in nanometer regime, the evolving nanotransistors are the promising alternatives to the planar MOSFETs. Nanotransistors reduce the short channel effects with improved device performance in terms of reduced power supply, power dissipation, leakage currents and improved scalability. This paper discusses about the challenges for scaling the transistors in nanoscale regime and also gives an insight on various types of emerging nanotransistors.
2000, IEEE Transactions on Electron Devices
2000, IEEE Electron Device Letters
2016
As the dimensions of transistors shrink, the close proximity between the source and drain reduces the ability of the gate electrode to control the potential distribution and the flow of current in the channel region because of which undesirable short channel effects starts plugging in MOSFETs. For all practical reasons, it seems to be impossible to scale the dimensions of classical bulk MOSFETs below 20nm. To satisfy Moore’s law in nanometer regime, the evolving nanotransistors are the promising alternatives to the planar MOSFETs. Nanotransistors reduce the short channel effects with improved device performance in terms of reduced power supply, power dissipation, leakage currents and improved scalability. This paper discusses about the challenges for scaling the transistors in nanoscale regime and also gives an insight on various types of emerging nanotransistors.
International Journal of Science Technology & Engineering
FinFETs have emerged as the solution to short channel effects at the 22-nm technology node and beyond. Here, the effect of fin shape on the leakage currents like Gate Induced Drain Leakage and subthreshold leakage is evaluated. The fin shape can be changed by varying the top width of the fin. Hence, the leakage currents are verified using their expressions for both rectangular and triangular FinFETs. The effects of oxide thickness, drain doping concentration and mobility on these leakage currents are also studied.
2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference
In this paper, we show that the subthreshold current–voltage characteristic can be used for estimating the interface trap density as a function of the energy in fully depleted symmetric metal-oxide-semiconductor devices with a minimum amount of modeling. The method is analyzed using TCAD simulations, and illustrated with the measurements on n-type silicon-on-insulator FinFETs. The results indicate that the trap density can be extracted between ∼0.65 and 0.90 eV. This range is limited by resolution issues at the lowest current levels, and by the transition from subthreshold to saturation behavior at the high current levels.
This paper assesses one Transistor Floating Body Random Access Memory (1T-FBRAM) in Bulk FinFET devices as a candidate for conventional DRAM replacement in the future technology nodes. For the cell operation, Bipolar Junction Transistor (BJT) programming is used. Reliability and retention time of the floating body effect are studied on different gate lengths, fin widths and for different programming biases. The degradation mechanisms during cycling are identified. The optimum number of cycles extracted (~109) is still far below the 1016 cycles expected. Long retention times are obtained; however, with the tail bit distribution below the 64ms DRAM specifications. Besides, the generated floating body takes place beneath the drain at the n+/p+ drain/ground-plane junction, which explains the long retention times by the large junctions area. Moreover, the floating body can be obtained only by leaving floating the bulk contact of the bulk FinFET cell, which makes its integration in a DRAM...
2008, Thin Solid Films
2017
The total ionising dose (TID) effects on different gate oxide used in silicon on insulator (SOI) FinFET are investigated in this paper. The device structure under consideration shows a three-dimensional (3-D) architecture of Silicon on Insulator (SOI) 30nm n-channel FinFET with a high-k hafnium oxide (HfO2) and aluminum oxide (Al2O3) as gate electrode. To test the influence of TID on the FinFET device the 3-D simulations were performed in Visual TCAD using radiation dedicated code for different gate oxides. The TID effects modify the electrical properties leading to deterioration of the device and failure of the systems associated with them. The influence of dose rate on the build-up of fixed charge in the gate oxide region and the interface charge at the oxidesemiconductor interface was analyzed and observed its impact was observed on the device characteristics. It has been found that oxide trapped charge density is higher than interface trapped charge density. As a result of TID, ...
IEEE Access
American Journal of Engineering and Applied Sciences
2008, Solid-State Electronics
CHAPTER OBJECTIVES How the MOSFET gate length might continue to be reduced is the subject of this chapter. One important topic is the off-state current or the leakage current of the MOSFETs. This topic complements the discourse on the on-state current conducted in the previous chapter. The major topics covered here are the subthreshold leakage and its impact on device size reduction, the trade-off between I on and I off and the effects on circuit design. Special emphasis is placed on the understanding of the opportunities for future MOSFET scaling including mobility enhancement, high-k dielectric and metal gate, SOI, multigate MOSFET, metal source/drain, etc. Device simulation and MOSFET compact model for circuit simulation are also introduced. etal-oxide-semiconductor (MOS) integrated circuits (ICs) have met the world's growing needs for electronic devices for computing, communication, entertainment, automotive, and other applications with continual improvements in cost, speed, and power consumption. These improvements in turn stimulated and enabled new applications and greatly improved the quality of life and productivity worldwide.